Author: Keith Evans
Date: 10:10:20 04/04/02
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On April 04, 2002 at 04:07:42, Tom Kerrigan wrote: >I know that simple, pipelined, carefully floorplanned, general-purpose CPU >designs run at ~100MHz on modern FPGAs. From what I know of the >Belle/Chiptest/DT/DB move generator, I'd expect its critical paths to be at >least twice as long, and probably longer. So I'd put an optimistic upper bound >of 50MHz on it. And that's just the move generator; I'd expect the eval logic to >be slower. But if you take the optimistic 50MHz number and the very overly >optimistic 2-cycle-per-node number, you get 25M NPS, not "30M NPS easily." > Let's brainstorm a little here - is there any way that we can use N move generators in parallel to increase the effective operating speed? What if one generator were to generate moves for the top half of the board, and another were to generate moves for the bottom half of the board? Any idea how much this changed move ordering would affect the size of the search tree? We could also have one evaluator dedicated to each move generator. This arrangement would be different than truly parallel search engines, and I'm curious about what efficiency we could expect. Probably the only way to tell would be to run some experiments. Anyways rather than worry about having a machine that can match Deep Blue's performance, a nice first step would be to have a machine that can beat Diep regularly ;-) Regards, Keith
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