Author: Keith Evans
Date: 10:52:53 04/04/02
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On April 04, 2002 at 13:19:02, Robert Hyatt wrote: > >He said that each "board" (which had 16 processors I believe) would have a >local shared hash table... IE each of the 16 processors would share a common >hash table with every other processor on the same board. But not between >boards. > >But even without sharing between the 16 chess processors, this would have been >yet another big gain in performance, just having hash tables, period... IE >the original Belle machine had a hash table as did the hardware box "BeBe"... It should be possible to directly interface to an external SDRAM DIMM which would enable a reasonably large hash table. (I just mention SDRAM because we built a 40 mbs data recorder using such a technique and it was quite easy to do.) If you just used on-chip FPGA RAM you would be limited to a hash table with only thousands of entries. The problem would be the latency to perform a read because I would think that every hash table read would require a random SDRAM cycle - which is no different than what's done on PC programs. This would probably take as long as a slow hardware evaluation cycle. (I would think that it's much quicker than a software evaluation.) My gut feel would be that it would still be a win because of how much less searching would be done given a reasonably high hit rate, but I don't know how to quantify it at this time. Regards, Keith
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