Author: Tom Kerrigan
Date: 19:53:53 04/04/02
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On April 04, 2002 at 13:25:59, Robert Hyatt wrote: >>On April 03, 2002 at 17:49:58, Robert Hyatt wrote: >>>ASICS used in the original DB hardware... 3 micron ASICS in DB only ran at >>>24mhz. An FPGA can certainly be run at that clock speed... > >I didn't write very clearly. Chiptest and deep thought (the original deep >blue hardware) was, I believe, 3 micron. DB1 and DB2 were complete re-designs >using smaller die sizes. This is mentioned in his book, when/if it comes >out... It's not that what you wrote wasn't clear, it was simply wrong. "3 micron ASICS in DB..." >>be slower. But if you take the optimistic 50MHz number and the very overly >>optimistic 2-cycle-per-node number, you get 25M NPS, not "30M NPS easily." >All I really know about the DT chip was that it took 10 cycles per node... >although some cycles were skipped (fast vs slow eval for example)... I based >the 30M nps value on statements made by Hsu... Statements made by Hsu about ASICs, not FPGAs. I cannot stress enough how completely different the two are. IIRC, DB could do a fast eval of a node, which took 2 cycles, and a slow eval, which took 8 cycles. It occurs to me that the DB chips were running at ~25MHz with the same feature size as the 200MHz PPro. With CPUs running at ~100MHz in FPGAs, you might expect FPGA chess logic to be half as fast as the DB ASICs, i.e., ~1M NPS. So while FPGA chess is a very interesting project, I'm not sure I'd expect it to be any faster than chess software. -Tom
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