Author: Keith Evans
Date: 16:56:25 04/05/02
Go up one level in this thread
On April 05, 2002 at 14:46:59, Robert Hyatt wrote:
>On April 05, 2002 at 04:31:54, Tom Kerrigan wrote:
>
>>On April 05, 2002 at 00:36:03, Robert Hyatt wrote:
>>
>>>And it is pretty easy to interpret "early DB hardware" as either deep thought
>>>hardware or DB1 hardware... Since the whole "line" was finally known as "deep
>>>blue"...
>>
>>These are quite the semantic contortions you're going through. If you need to be
>>right so bad, fine.
>>
>
>What is "right" here? I simply explained _my_ statement which was written
>rather loosely. There is no "right" or "wrong" in this context. It was
>simply a clarification of what I meant.
>
>Seems pretty obvious that "early deep blue hardware" meant something other
>than "deep blue hardware"...
There's a paper written by Hsu, Campbell, and Hoane in June of 2001 which
describes the machines as follows (I'll paraphrase to keep it short):
ChipTest and Deep Thought
Developed at Carnegie Mellon in the 1980's
Used a single chip chess move generator
Deep Thought 2 aka Deep Blue Prototype
Developed at IBM T.J. Watson Research Center
Used the same old single chess move generator
Personal note - _still_ not "Belle on a chip"
Improvements over Deep Thought as follows:
Medium-scale multiprocessing
Enhanced evaluation hardware (larger RAMs and eval func)
Improved search software
Extended book
Deep Blue I
Based on a single-chip chess search engine developed over the
course of 3 years. Revised chips (final?) received Sep 1995)
36-node IBM RS/6000 SP
Personal note - so in 1995 we had the first chip which could
likened to a "Belle on a chip"
Deep Blue II
Significantly enhanced chess chip
Double the number of chess chips in the system
Newer generation SP
>>>I think it would _clearly_ be faster than software... IE DB took ten clocks
>>>per _node_. What software program comes anywhere near that. More like
>>>3000 instructions per node, which turns into 4-5000 clocks most likely.
>>
>>Right, and when your chip runs at 12MHz, 10 cycles = 833 ns = 1666 cycles =
>>nearly 2000 instructions with a 2GHz MPU. If you want to point out flaws in the
>>way I estimated the FPGA's performance, go for it. But you're not going to
>>convince me of anything by saying that software can't evaluate nodes in 10
>>cycles. That's obvious to anybody.
>>
>>-Tom
>
>I think you pointed out the flaw yourself. 2000 instructions at 2ghz is not
>_nearly_ enough to do a node. And a 12mhz FPGA is a very slow FPGA. 100mhz
>is more like it for SOTA... I'll take on that 2ghz general-purpose CPU any
>time you want...
I don't know of any way to pipeline the move generator, and currently don't have
any idea about implementing eval comparable to what Deep Blue II had. So let's
scale back the 100 MHz to 33 MHz based on Marc's work, and assume that the eval
won't be any worse. If you meant a full custom 0.18 micron chip, then maybe 100
MHz is feasible. But I can't see anybody building that given the high costs
involved - maybe if Bill Gates were really into chess and thought that he could
get some good PR.
Nobody's going to get rich off of this, so some of the goals for such a project
would be to make the source available to everybody to learn the fine details
instead of just being able to read vague statements. For instance Hsu says the
his chips can generate checking moves - but it looks to me based on the signals
available (after Marc pointed it out) like there are certain cases where it
would generate a bishop move that would not actually be a checking move. Is this
true? If it is true then did Hsu realize it and filter such moves out somehow?
Or is this a weakness that could be exploited? Or merely a flaw in the paper
itself? How can I know this based on the published materials?
Hsu also says that his chips can generate discovered check moves - but in his
IEEE Micro he doesn't go beyond mentioning that he can identify which pieces
could generate discovered checks. How ugly is it to actually enumerate all of
the moves then?
I don't know what type of performace we'll ultimately achieve - achieving an ELO
higher than that of the major commercial programs would be a major feat. Keep in
mind that FPGAs are evolving and it will take time to complete development.
Eventually this will make sense, and then we'll be ready. I wouldn't want Brutus
to be the only player in this space.
Regards,
Keith
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