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Subject: Re: HW based Crafty (Boule's thesis)

Author: Robert Hyatt

Date: 19:09:03 04/06/02

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On April 06, 2002 at 00:53:39, Tom Kerrigan wrote:

>On April 05, 2002 at 14:46:59, Robert Hyatt wrote:
>
>>Seems pretty obvious that "early deep blue hardware" meant something other
>>than "deep blue hardware"...
>
>Yeah, except you said "original," not "early." Do you consider Chiptest
>"original DB hardware"? Because I don't.

I certainly consider "deep thought" to be "original deep blue hardware".

As does most everyone, since that is where it _started_...

>
>>There _is_ no "precise number".  There were three complete revisions of the
>>chess processor.  I haven't seen anything that said all three had the same
>>number of cycles in each operation or that they didn't...
>
>So in other words, you don't know the numbers (because if you did, you would
>know whether or not they were the same). So your information-free replies
>continue to mistify me.
>
>>I think you pointed out the flaw yourself.  2000 instructions at 2ghz is not
>>_nearly_ enough to do a node.  And a 12mhz FPGA is a very slow FPGA.  100mhz
>>is more like it for SOTA...  I'll take on that 2ghz general-purpose CPU any
>>time you want...
>
>First, my own program would search more than 1M NPS on a 2GHz chip. Which means
>fewer than 2k cycles per node. Which means ~2k instructions per node, and
>possibly less. Which means that not only are 2k instructions "nearly" enough to
>do a node, they ARE enough to do a node.

I believe I said a "real chess program"...  I don't know of any "real" engines
that search 2K instructions per node...  I'm also talking about _real_ nodes...
Just to be clear...



>
>Second, what the hell are you talking about with regard to FPGA speeds? "A 12MHz
>FPGA is a very slow FPGA"? It's easy to come up with some logic that would run
>at less than 1MHz on the fastest FPGA ever. Your apparent notion that FPGA clock
>speed is somehow independent of the design that's loaded into the FPGA speaks
>volumes about your ignorance of what an FPGA actually is.
>
>-Tom


If that is as _fast_ as the specific FPGA you want to use can be clocked,
then _yes_ it is "very slow".

Nothing more to say...  There are parts available for a year or more that
run over 75mhz...  A FPGA certainly has a max clock speed regardless of _what_
is "loaded into it".  This clock speed might be significantly lower due to the
thing being "loaded" of course.  But there _is_ a max no matter what is loaded,
and _that_ is the raw speed number I was referencing..  Everything has a max
due to various things from gate delays to whatever you want..



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