Author: Keith Evans
Date: 10:19:04 04/09/02
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On April 09, 2002 at 00:46:11, Tom Kerrigan wrote: >On April 08, 2002 at 23:58:40, Keith Evans wrote: > >>One nice thing about a bitboard accelerator is that it could probably be >>pipelined and clocked reasonably fast. One problem is that the placement of the >>RAMs is fixed - so routing delays may be large depending on how the tables are >>used. > >How do you figure, about the pipelining? > >I don't understand why "accelerating bitboards" is interesting. What bitboard >operation is expensive enough to warrant the 33MHz bottleneck? I can't think of >any. > It sounded to me like some of the operations were multicycle - so the pipelining thing was just a guess and a hope. It's sort of frustrating that a Belle style move generator can't be pipelined, and it would be interesting to find another approach which could be pipelined and make sense for something like an FPGA. The move generator isn't the bottleneck, but it's just irritating nevertheless. To be honest the complete chess engine is much more intellectually interesting to me, but if there's an easier way to get some amount of performance increase then I'm not against thinking about it too. I'm not one of those guys wanting to put a general purpose CPU into an FPGA however. Would have been fun to do back in college though. Keith
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