Author: Jeremiah Penery
Date: 06:09:11 05/12/02
Go up one level in this thread
On May 12, 2002 at 07:18:07, Vincent Diepeveen wrote: >On May 11, 2002 at 13:14:02, Jeremiah Penery wrote: > >>On May 11, 2002 at 09:38:15, Vincent Diepeveen wrote: >> >>>For a 64 bits cpu to be interesting for chess they need to do something >>>no one ever has managed before. >> >>And that is...? The Alpha seems pretty nice, as well as POWER4, according to >>SPECInt numbers (for Crafty). Just because they aren't good for DIEP doesn't >>mean they can't be good for chess. You don't even use 64-bit variables in DIEP >>(right?), so why would you expect a 64-bit chip to be any faster for you? > >i'm using 'int' so if a compiler rewrites that to 64 bits, then it's >DIEP is a 64 bits program. No it's not. You're going to have half those bits filled with zeros, so it's irrelevant. >a 64 bits cpu is completely different from 32 bits. it's not an 'extension'. >Because 'extensions' are hell slower. x86-64 is pretty much an 'extension' of x86-32. >The compiler is not such a trivial thing. If you get 256 registers >instead of EAX,EBX,EXC and another few others (with another 44 extra >registers to use for register renaming etc) then the importance of the >compiler is major. > >All the speedup has to come out of the compiler, *not* out of different >programmed software of course. The compiler is important, but it's not going to be a huge thing to make a compiler that emits decent x86-64 code, since it will be so close to existing x86-32 code. It's not like it has 256 new registers to deal with - there are only 8 more GP registers to deal with, and the fact that registers now hold 64 bits. >DIEP was very slow on the first alpha's, which is very irrelevant for >the blazing fast plans that are on the board for Hammer and McKinley. Have you even read the documentations for IA-64? >On paper diep should be very fast on McKinley and Hammer. In reality however >both chips are not comparable. McKinley is 2 generations newer design >than Hammer is. And the compiler for McKinley will be about 6 generations behind. :) >Suppose all AMD does is extend their FPU/MMX thing with >some extra instructions. Then you have like 8 general MMX registers. > >That's not worth the effort of course. > >They need to make 128+ at least easily accessible 64 bits registers >at least to make the chip interesting. Then they STILL are a generation >behind on the McKinley. Do I need to keep asking if you've even read the documentation? x86-64 makes 16 64-bit general-purpose registers available. It also adds some MMX/SSE/SSE2 registers. >With so many registers the importance of the compiler gets overwhelming. > >It's more than a factor 2 a good compiler on such a chip. > >There are more issues. How big is the size of this chip going to get? Hammer is supposed to be some 103mm^2. McKinley is 464mm^2. >Now the most important question: how high can they clock such a chip? > >The current plans on paper are simply not realistic. Are you talking about Hammer here, or McKinley?
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