Author: Jeremiah Penery
Date: 10:47:00 05/12/02
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On May 12, 2002 at 06:42:27, Vincent Diepeveen wrote: >On May 12, 2002 at 00:31:51, Martin Andersen wrote: > >And it is called McKinley and on paper it's impressive >what it delivers a Mhz. > >just a few details i remember: > 1Ghz , 3MB L2, The cache number is wrong. Itanium (and McKinley) have only 32KB of L1 cache (16KB code/16KB data). Itanium has 96K of L2 cache, McKinley has only 256K of L2. The 3MB is L3 cache, which is on-chip, with 12-cycle access in McKinley (20 cycles in Itanium). > 6 instructions a clock, Theoretically it can execute this, but hardly ever in practice (on integer code). The reason is that the instructions must be bundled in groups of 6, and that Itanium is an _in-order_ processor. If there aren't 6 instructions it can bundle together, it has to issue a bunch of no-ops in the bundle. In addition, the compiler technology for IA-64 is very immature. I'm sure with better compilers they will be able to come closer to that theoretical limit. > not extreme penalty however for misprediction, loads of registers, and a big L1 cache. There is very little penalty for misprediction, since it has full hardware predication. It also has a ton of registers, but it can only access 128(?) at a time, and the rest it can get through a large rotating register file, which may have some penalty associated with it, I don't remember specifically. As I said above, the L1 cache is actually very small. >What do you need more? > >The first cpu was of course not so fast, but making it already was enough >to impress the world because of the price a cpu intel can make it for. I'm not sure what you're talking about here. The Itanium is a very big and very expensive processor.
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