Author: Eugene Nalimov
Date: 16:25:06 06/20/02
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PA-RISC 2.0 not only extends PA-RISC 1.1 to 64 bits. Some other differencies are: (1) Cache prefetch hints on the instructions. (2) Branch prediction hints on the instructions. (3) Weaker memory model (not sure if that is relevant to the compiler, but it can cause huge slowdown if hardware really runs in the compatibilty mode). (1) and (2) can be exploited by the smart compiler, but probably not by gcc. (3) is another issue, if it is handled by the hardware. Eugene On June 20, 2002 at 18:49:01, Tom Kerrigan wrote: >On June 20, 2002 at 18:24:14, Robert Hyatt wrote: > >>On June 20, 2002 at 17:58:20, Tom Kerrigan wrote: >> >>>On June 20, 2002 at 17:42:30, Dann Corbit wrote: >>> >>>>Do you imagine that this will settle any argument beyond that particular >>>>CPU/OS/compiler combination? >>>>I don't. >>> >>>Why not? gcc is gcc. The HP-PA is your standard RISC chip. The OS doesn't >>>matter. I don't see why the HP-PA would get more or less of a speedup going to >>>64-bit than a MIPS, UltraSparc, POWER, or any other RISC chip. >>> >>>-Tom >> >> >>Check out the optimizer. It behaves differently for different chips. It >>does some well (intel). It does some horribly (sparc). > >Wouldn't it do consistently well or consistently badly? Then you still know the >relative advantage of the 64 bit datapath. > >-Tom
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