Author: Robert Henry Durrett
Date: 05:49:15 06/24/02
Apparently, "memory bandwidth" limitations result in chess computer performance limitations. I don't really understand the details, but it's supposed to be true. In fact, I don't really understand "memory bandwidth." I assume it is some sort of limitation on how fast information can be written to or retrieved from RAM. Presumably, new technology would improve this. Do I have this right? So, the logical solution seems to be to minimize the number of times the program has to "go to memory," which I interpret as "going to RAM." It would seem that extensive use of caches would help in that regard. Someone pointed out recently that it takes only a few clock cycles to read or write to a cache [depending on which cache] but takes a huge number of clock cycles to do that with RAM. Now they're saying that the new Intel Itanium microprocessors have huge caches. [Also huge prices!] Doesn't this suggest that judicious use of huge caches [in preference to RAM] would produce better chess engines? This assumes that there is a way for the programmer to actually accomplish this. The right compilers must be used. If anybody here understands this stuff, please explain everything. :) Summary: Bigger caches mean better chess engines? Bob D.
This page took 0.01 seconds to execute
Last modified: Thu, 15 Apr 21 08:11:13 -0700
Current Computer Chess Club Forums at Talkchess. This site by Sean Mintz.