Author: Gian-Carlo Pascutto
Date: 06:48:14 06/24/02
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On June 24, 2002 at 08:49:15, Robert Henry Durrett wrote: > > >Apparently, "memory bandwidth" limitations result in chess computer performance >limitations. I don't really understand the details, but it's supposed to be >true. In fact, I don't really understand "memory bandwidth." I assume it is >some sort of limitation on how fast information can be written to or retrieved >from RAM. Presumably, new technology would improve this. Do I have this right? > >So, the logical solution seems to be to minimize the number of times the program >has to "go to memory," which I interpret as "going to RAM." It would seem that >extensive use of caches would help in that regard. > >Someone pointed out recently that it takes only a few clock cycles to read or >write to a cache [depending on which cache] but takes a huge number of clock >cycles to do that with RAM. > >Now they're saying that the new Intel Itanium microprocessors have huge caches. >[Also huge prices!] > >Doesn't this suggest that judicious use of huge caches [in preference to RAM] >would produce better chess engines? This assumes that there is a way for the >programmer to actually accomplish this. The right compilers must be used. > >If anybody here understands this stuff, please explain everything. :) > >Summary: Bigger caches mean better chess engines? The programmer doesn't have to do anything to make use of the caches of the CPU's. The cache is simply a faster kind of memory. If the program reads something from (slow) RAM, the cache will remember that information. The next time the program wants to read that value, the cache can return it and the program does not have to wait for the RAM. This is all handled by the CPU, i.e. no additional effort for the programmer. As far as I know, memory bandwith is _not_ a limiting factor of most chess-engines, but memory latency is. Caches will help with that as well. -- GCP
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