Author: Robert Hyatt
Date: 10:07:33 08/11/98
Go up one level in this thread
On August 11, 1998 at 11:23:15, Moritz Berger wrote: >Posted by fca on August 11, 1998 at 08:45:55: >> >>In Reply to: Re: [Q] What is Genius' speed? posted by Tom Kerrigan on August 11, 1998 at 08:06:36: >> >> >>On August 11, 1998 at 08:06:36, Tom Kerrigan wrote: >> >>>Aside from software differences, the Pentium MMX/200 has a 66MHz L2 cache >>>(possibly smaller than 512k) whereas the Pentium II/300 has a 512k 150MHz L2 >>>cache. >> >>Are you sure, Tom? I thought the 1/2 speed clock for the L2 only applied to >>P2's of 350MHz or faster (excepting Xeons, which are of course full speed >>L2-ers). If so, 100 MHz >> 66 MHz > >PII 2nd level cache speed frequency = core frequency / 2 for all PII (i.e. >PII-233 2nd level cache at 116.5 Mhz) > excepting the new PII/Xeon, which runs L2 at core speed... Leave it to Intel to completely screw up naming conventions... why the PII/Xeon wasn't called something else is anybody's guess... >>>If a program really bangs on the L2 cache, it will go much faster on the >>>Pentium II. >> >>Surely. Let us test that this is the cause for the differences blass reports. >> >>(a) Does it follow in broad terms that the higher the nps, the more hash >>activity (but what about other tables?), therefore more L2-dependence (L1 deemed >>to be too small to have too much influence)? > >Higher NPS -> higher memory throughput -> less cache efficiency (just imagine a >program that uses e.g. 64 KB hash and "lives" completely in the 512 KB 2nd level >cache of a PII in comparison with Fritz which fills up hundreds of megabytes of >hash tables in a couple of minutes). > yes, but hash probes are almost *never* done, when considering the total number of words accessed. IE we probe exactly once per node, where a node takes at least a couple of thousand instructions, which turns into 1.5-2x that in memory references. So the hash table doesn't really count in the speed of things... >>(b) Is the P2/300 : P200MMX ratio even higher for F5 (which I take it is >>accepted is significantly higher in nps terms than J?) > >Junior 5 peaks out at slightly above 400kN/s on my PII400. So it's not >"significantly" slower in terms of NPS than Fritz 5. > >>If answer for (a) is Yes and answer for (b) is No, the cause is liable to be >>something else. > >Something else could be: >a) 16 bit code vs. 32 bit code >b) optimization for P5 pipelines (superscalar design, executing multiple >instructions at once) >c) segment boundary alignment (affects P5 and P6 not in the same way) >d) branch prediction logic of the CPU, assumptions about this in hand crafted >assembler code >e) use of certain "string" (i.e. affecting a sequence of bytes) instructions and >preferred primitive data types (32 bit integers, 16 bit integers, etc.) - P5 and >P6 speed optimizations are often mutually exclusive actually, in the P6, there is very little you can to to hurt it. IE it will execute a program compiled for a 386/486 (no super-scalar pairing done at all) far faster than a regular pentium will, because the P6 will "pool the instructions" and then pair them at will, regardless of how they are mixed. It also does register renaming to reduce conflicts between instructions so that they are even easier to "pair" automatically... >f) e.g. using the FPU to initialize hash tables - more than 2x faster on a P5 >than using integer moves, about as fast on PII, much worse on K6. >g) add your own favourite difference in processor architectures of P5 (Pentium, >Pentium MMX) and P6 (Pentium Pro, PII) > >Saludos > >Moritz > >P.S: Even different steppings (read: releases) of the Pentium MMX exhibit >massive differences in execution speed of certain commands (stepping 4 several >times slower (on some commands) than stepping 3 comes to my mind), so that's >another distracting factor we have to take into account. Intel has always been wonderful there. :)
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