Author: Tom Kerrigan
Date: 11:08:15 08/12/98
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On August 12, 1998 at 10:58:17, fca wrote: >SUMMARISED VIEW OF FCA: As long as L2 size/speed keep up with "core MHz ratios >times allowance for P-->P2 ", it is not relevant when trying to explain >differences in performance of (say) Junior on a P200MMX and a P2/300. Yes, I disagree. "Core improvements" doesn't simply mean that instructions are executed faster. The P6 core is designed to be less dependent on the L2 cache, too. The obvious example here is the Celeron, which doesn't have ANY L2 cache, and it still manages to keep pace with a Pentium MMX/233 with 512k L2 cache. -Tom
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