Author: Dann Corbit
Date: 18:03:08 08/19/02
Go up one level in this thread
On August 18, 2002 at 22:59:35, Robert Hyatt wrote: >On August 17, 2002 at 14:26:55, Vincent Diepeveen wrote: > >>On August 17, 2002 at 12:45:04, Uri Blass wrote: >> >>>On August 17, 2002 at 12:35:52, Dan Andersson wrote: >>> >>>>Pretty sure of yourself, are you? Would be interested to see you prove your >>>>statement. One thing first, how do you define bitboards? >>>> >>>>MvH Dan Andersson >> >>That is not enough. If nearly all of your evaluation code is >>using a 64 bits bitboard based approach then i would vote for >>it being called a bitboarder, if vaste majority >>of code would work on 32 bits processor too, then it's obviously >>a non-bitboarder. >> >>Any other form is a 'mixture'. >> >>BTW, i wonder how i get a bit out of a bitboard at the R14000 >>processor. How's crafty doing that? Or probably crafty never >>compiles on the thing without using zillions of branches for its > >Perhaps you should _look_ first. Intel has an instruction to do this. Cray >has one. Alphas have one. Are you _sure_ MIPS didn't do one? I don't have >any docs here, but you might be surprised... Format: DCLZ rd, rs MIPS64 Purpose: To count the number of leading zeros in a doubleword Description: rd ¬ count_leading_zeros rs The 64-bit word in GPR rs is scanned from most significant to least significant bit. The number of leading zeros is counted and the result is written to GPR rd. If no bits were set in GPR rs, the result written to GPR rd is 64. Restrictions: To be compliant with the MIPS32 and MIPS64 Architecture, software must place the same GPR number in both the rt and rd fields of the instruction. The operation of the instruction is UNPREDICTABLE if the rt and rd fields of the instruction contain different values. Operation: temp <- 64 for i in 63.. 0 if GPR[rs]i = 0 then temp <- 63 - i break endif endfor GPR[rd] <- temp Exceptions: None 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL2 011100 rs rt rd 0 00000 DCLZ 100100 6 5 5 5 5 6 Count Leading Zeros in Doubleword DCLZ Some MIPS CPU instructions that would be useful for bit operations: CLO Count Leading Ones in Word CLZ Count Leading Zeros in Word DCLO Count Leading Ones in Doubleword DCLZ Count Leading Zeros in Doubleword DSLL Doubleword Shift Left Logical DSLL32 Doubleword Shift Left Logical Plus 32 DSLLV Doubleword Shift Left Logical Variable DSRA Doubleword Shift Right Arithmetic DSRA32 Doubleword Shift Right Arithmetic Plus 32 DSRAV Doubleword Shift Right Arithmetic Variable DSRL Doubleword Shift Right Logical DSRL32 Doubleword Shift Right Logical Plus 32 DSRLV Doubleword Shift Right Logical Variable SLL Shift Word Left Logical SLLV Shift Word Left Logical Variable SRA Shift Word Right Arithmetic SRAV Shift Word Right Arithmetic Variable SRL Shift Word Right Logical SRLV Shift Word Right Logical Variable AND And ANDI And Immediate LUI Load Upper Immediate NOR Not Or OR Or ORI Or Immediate XOR Exclusive Or XORI Exclusive Or Immediate
This page took 0 seconds to execute
Last modified: Thu, 15 Apr 21 08:11:13 -0700
Current Computer Chess Club Forums at Talkchess. This site by Sean Mintz.