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Subject: Re: Who can update about new 64 bits chip?

Author: Robert Hyatt

Date: 15:08:47 08/26/02

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On August 26, 2002 at 16:35:10, Bo Persson wrote:

>On August 26, 2002 at 11:07:25, Robert Hyatt wrote:
>
>>On August 26, 2002 at 05:13:35, Vincent Lejeune wrote:
>>
>>>
>>>Waiting for the real numbers ...
>>
>>
>>Read that again, carefully.  "local memory". This is NUMA.  The penalty for
>>accessing memory that is _not_ local is significant.  The penalty for accessing
>>local memory is still 100ns or so, because nobody knows how to reduce
>>resistance, capacitance and inductance together.
>>
>>When you have multiple processors there will be significant conflicts.  I don't
>>know whether that "hypertransport bus" if full-duplex or not.  If it is, it
>>might work OK for two processors, but not beyond two as there would be no easy
>>way to manage more than two.
>
>Theoretically they could. The more-than-2-way Hammers, the Opteron, have 4 sets
>of the hypertransport logic. Would work fine for quad boxes. The local memory
>channel is also separate. They have a *lot* of pins...

OK... If they do 4 channels.  This sounds like a transputer approach of
course, where beyond 4 you run into the same problem as always if you only
have four connections to play with...  Then you can try hyper-cube type
approaches to use 16 nodes and 4 connections I suppose..  with more latency.

>
>> I assume it is a "normal bus" which means if
>>the two processors want to access each other's local memory, one is definitely
>>going to wait.  And that also means there is some sort of bus negotiation
>>protocol which extends latency as well...
>
>Probably!
>
>
>Bo Persson
>bop2@telia.com



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