Author: Jeremiah Penery
Date: 18:33:18 08/26/02
Go up one level in this thread
On August 26, 2002 at 15:06:05, Robert Hyatt wrote: >On August 26, 2002 at 13:12:42, Jeremiah Penery wrote: >>On August 26, 2002 at 11:16:47, Robert Hyatt wrote: >>As I said, much of that time must come from the long travel path, slow memory >>controller, etc. > >We just disagree on where the delay is. I believe that at _least_ 80% of >the latency is in the chip. Not in the controller/bus... >>If you see 140ns today (average), you don't believe that almost half of that >>latency is caused by the travel path from CPU/controller/memory and back? If >>the memory controller runs at bus speed (133MHz), it has 7.5ns/clock cycle. >>That alone is significant latency added to the process. > >I don't believe it, no. I believe that most of the latency is in the DRAM >itself, not in the controller. The controller has no "capacitors" to deal >with, it is made up of SRAM buffers and some form of hardware logic (such >as TTL) which means switching times are at the picosecond level. It takes >a _bunch_ of picoseconds to add up to a nanosecond... The clock cycle of the memory controller is some 7.5ns. It can only send one request/clock, AFAIK. That is already adding significant latency. >>Even a few 10s reduces your number of 120ns to the claimed 80ns of Hammer. :) > >I'll believe 80 when I actually get my hands on it. :) Because that will >be faster than any Cray ever made (that used DRAM, older crays used bipolar >but the memory was not nearly as dense). >I was talking about cray from the perspective that they have never had an 80ns >memory access time. It has _always_ been over 100 since they moved away from >bipolar memory to DRAM for density. And their controllers have >_never_ "sucked" It's difficult to find really accurate data on this. I've read more than a few different things. But from what I can tell, the latency (cycle time) of DRAM c. 1994 was on the order of 100ns. (In 1980, it was 250ns; 1989 was nearer 170ns). It hasn't been lowered at that pace since then, but it has gotten lower. As I've said, current figures I've seen place it at 70ns today. _Any additional latencies_ seen are/were caused by controller, path length, and whatever else. If you don't think path length can influence latency very much, then you must not talk about RDRAM having bad latency. :) The only reason it has higher latency is because of a much longer path length for the memory request signal. (And sometimes the banks can go into sleep mode, and take a while to wake.) Cray machines probably have some additional issues because they're super-multi-ported designs, with a lot of processors trying to concurrently access the same memory banks. (I'm talking about their vector machines, not stuff like the T3E, which is some kind of Alpha cluster.)
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