Author: Ed Panek
Date: 07:08:29 08/27/02
http://www.theinquirer.net/?article=5134
SIS' Hammer plans disclosed
And support for Intel's 667MHz FSB
By Mike Magee: Tuesday 27 August 2002, 06:55
A PAGE AT Japanese site PC Watch has some pictures up of
roadmaps from Silicon Integrated Systems (SIS), and its 755/963
system architecture.
The pics show Hammer CPUs as having a 800MHz front side bus
and include other details of the support its chipsets will
have.
Is the 800MHz FSB a typo, that is the question? It is probably
just
"roadmap shorthand" for the speed the Hypertransport bus runs
at,
we think.
Those include DDR 200, 266 and 333 support, for 1GB per DIMM
and for two unbuffered or four registered DDR modules.
For its 755/963 combo, the bi-directional Mutiol bus will run
at
1GB/s, while its chipset will support three 1394A ports, dual
IDE,
sound, and a number of other features including AGP 3.0 8X.
There's also details of its 760/963 architecture on the site,
in the
shape of a slide.
The first slide on the page reveals some details of both its
AMD
and Intel chipset plans, including support for the Intel 667
bus with
DDR-II, which comes next year, and for the Dual RDRAM chipset
using PC-1333 which we wrote about a little while back.
The same page has a handy little table outlining its different
chipset
directions.
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