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Subject: Re: Thesis by Marc Boule

Author: Marc Boulé

Date: 17:25:56 09/07/02

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>On September 07, 2002 at 19:01:58, Marc Boulé wrote:
>
>>
>>>Marc - thanks for remembering.  :)  I have spent 100's of hours reading
>>>articles, asking questions, and studying.  It's coming.  I am still working on
>>>it.  I have not given up.  I will try my best to have a HW based computer chess
>>>program playing on ICC by Christmas.  :)
>>>
>>>(Expect a 1,000 question e-mail; it's coming - I've been saving up!)
>>
>>lol!
>>
>>bring the heat...
>>
>>Marc Boulé
>
>Marc,
>
>Nice work, I read the condensed article.  A couple questions:
>
>You indicated the move-order was helped by a centrality term.  Does this have a
>similar effect for your software-only version?
>
>Would the fpga be fairly straightforward to interface to the average chess
>program?  Have others tried it?
>
>And lastly, do you have plans to extend the work to the search and eval?
>
>Will

Here's the centrality part you're talking about (From ICGApaper.pdf), my
comments are below:

"Another improvement regarding the arbiters has also been developed. Arbiter
centrality is used to describe the pattern in which the arbiters are connected.
With a regular interconnect pattern, priority between equal voting squares is
broken with location. After captures are finished, moves would be ordered from
top-right to bottom-left. However, because of the center bias present in the
positional evaluation function, arbiters are rearranged to prioritize the center
squares. This increases the quality of the move ordering and further reduces the
number of nodes searched."

This is a hardware-only feature because it affects the interconnect pattern of
the hardware arbitration tree. To get the same effect in software, one would
have to sort the move list so that equal valued moves are ordered from the
center toward the edges of the board. I didn't test this becasue of the
computation overhead it introduces, but I think it would be an interesting
experiment. In HW, centrality is virtually "free".

In order to interface the chess FPGA to other programs, you need to understand
the host program very well. Move generation is so intertwined with the rest of
the chess engine that replacing software calls with hardware calls is not
obvious. I don't know of anyone who has done this yet. In my case, the
integration is even harder because I didn't write sufficient documentation :-(.
I guess that with enough patience and effort, it can be done.

I probably will not be continuing with hardware eval and search but Slater might
be exploring this area in the near future.

Marc Boulé



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