Author: Vincent Diepeveen
Date: 10:21:49 09/08/02
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On September 07, 2002 at 20:02:29, Marc Boulé wrote: Are you in verilog at FPGA? Any previous experiences in verilog and the donated board, how many gates to you have at your disposal? Best regards, Vincent >>Well, when we first started talking I was actually on vacation. So a lot of the >>initial discussion between you and Keith I was unable to join on in. >> >>You and Keith have a huge lead on me, in that you both do this everyday. So I >>have spent most of the last 6 months trying to learn HDL and various aspects of >>hardware design. Everytime I learn something new, I have a new question for >>you. I have gathered quite a few over the last 6 months. However, I have >>answered a lot of my own questions just by learning more and more. Also, your >>thesis (which is great btw) has answered quite a few of them too. >> >>I just didn't want to "bother" you, because unlike Keith I didn't have anything >>to help your thesis, only questions about HDL and the like. >> >> >>By the way, what are you planning to do with MBChess? Are you going to continue >>to develop it, or is this a project your done with? Did you have to give the >>FPGA back, or do you still have it? Any plans on this front? > >MBChess is going on the shelf for the next 3 years as I am attempting a PhD in a >slightly different field (hardware-accelerated automated theorem proving). > >The FPGA was donated by Xilinx so I can keep it and my professor paid for the >board, which I will also keep. The board will next be used in the initial tests >for my doctoral project. > >Marc Boulé
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