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Subject: Re: Thesis by Marc Boule

Author: Vincent Diepeveen

Date: 13:52:17 09/08/02

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On September 08, 2002 at 16:09:30, Marc Boulé wrote:

how many gates do you estimate your move generator will cost you?

>>Are you in verilog at FPGA?
>>
>>Any previous experiences in verilog and the donated board,
>>how many gates to you have at your disposal?
>>
>>Best regards,
>>Vincent
>>
>
>I use VHDL to code hardware.
>
>I had previous experience with VHDL and FPGAs. A few undergraduate courses I
>took helped me alot. In the databook, the device says a total of 888k system
>gates but that's if you count the blockRAM and all. A more resonable metric for
>me is # of logic cells (1 LUT + 1 FF). In this case, approx 20 000 LCs.
>
>Marc Boulé



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