Author: Gerd Isenberg
Date: 08:40:38 09/27/02
Go up one level in this thread
On September 27, 2002 at 05:46:55, Gerd Isenberg wrote: >On September 27, 2002 at 04:57:10, Tim Foden wrote: > >>On September 27, 2002 at 04:48:03, Gerd Isenberg wrote: >> >>>from: >>> >>> AMD x86-64 Architecture >>> Programmer’s Manual >>> Volume 4: >>> 128-Bit Media Instructions >>> >>>=============================================================================== >>>PSLLDQ Packed Shift Left Logical Double Quadword >>> >>>Left-shifts the 128-bit (double quadword) value in an XMM register by the >>>number of bytes specified in an immediate byte value. The low-order bytes that >>>are emptied by the shift operation are cleared to 0. If the shift value is >>>greater than 15, the destination XMM register is cleared to all 0s. >>> >>>PSRLDQ Packed Shift Right Logical Double Quadword >>> >>>Right-shifts the 128-bit (double quadword) value in an XMM register by the >>>number of bytes specified in an immediate byte value. The high-order bytes that >>>are emptied by the shift operation are cleared to 0. If the shift value is >>>greater than 15, the destination XMM register is cleared to all 0s. >>>=============================================================================== >>> >>>Same instructions are already available on Intel's PIV with SSE2. >>>I'll hope that "is greater than 15" is a typo or erroneous copied from PSLLW. >>>It should be 127 here. >> >>If you read what it says... it shifts by a BYTE at a time, not a BIT at a time. >>So the maximum shift is by 15 BYTES. :) >> >>Cheers, Tim. >> > >Thanks, Tim. >Aha, Shifting bytewise? So there is no way to shift 128bits bitwise. >I love this stringent instructions. > >from >AMD x86-64 Architecture >Programmer’s Manual >Volume 1: >Application Programming > >Chapter 4: 128-Bit Media and Scientific Programming > >The PSRLDQ instruction differs from the other three right-shift >instructions because it operates on bytes rather than bits. It >right-shifts the 128-bit (double quadword) value in an XMM >register by the number of bytes specified in an immediate byte >value. PSRLDQ can be used, for example, to move the high 8 >bytes of an XMM register to the low 8 bytes of the register. In >some implementations, however, PUNPCKHQDQ may be a >better choice for this operation. > >Gerd A nice hint from: =============================================================================== IA-32 Intel ® Architecture Software Developer’s Manual Vol ume 1 : Basic Architecture 11.6.11. Updating Existing MMX Technology Routines Using 128-Bit SIMD Integer Instructions Use of the 64-bit shift by bit instructions (PSRLQ, PSLLQ) can be extended to 128 bits in either of two ways: — Use of the PSRLQ and PSLLQ instructions, along with masking logic operations. — Rewrite the code sequence to use the PSRLDQ and PSLLDQ instructions (shift double quadword operand by bytes). =============================================================================== So you have to do something like this, ... movdqa xmm2, xmm1 ; save operand to shift psllq xmm1, imm5 ; now we miss some (imm5) low bits in high quadword psrlq xmm2, 64-imm5 ; shift this bits right, that they become low bits pand xmm2, [imm5mask] ; eg for 9 0x0....01ff pslldq xmm2, 8 ; low quadword to high quadword por xmm1, xmm2 ; combine both, result in xmm1 ... to emulate "psllh xmm1, imm5 [1..63]" (packed shift left logigal hex, not available) to bitwise shift left an 128bit xmm register. A lot of additional effort, six instructions instead of one, the use of an extra register, one additional 16(8)-byte memory access. Only if ( imm8 % 8 == 0 ) one can use one "pslldq"-instruction. Therefore adapting dumb7fill or Kogge-Stone-Fill with "greater" boards (10*10, 10*9 mapped to 128bit BitBoard) seems difficult to me. http://www.talkchess.com/forums/1/message.html?253910 Regards, Gerd > >>>Can anybody confirm this for PIV? >>> >>>Regards, >>>Gerd
This page took 0 seconds to execute
Last modified: Thu, 15 Apr 21 08:11:13 -0700
Current Computer Chess Club Forums at Talkchess. This site by Sean Mintz.