Author: Robert Hyatt
Date: 07:05:38 10/13/02
Go up one level in this thread
On October 13, 2002 at 06:33:27, Gian-Carlo Pascutto wrote: >On October 12, 2002 at 18:49:41, James T. Walker wrote: > >>They would >>have to be getting almost 100% efficiency out of the 8 cpus to hit 3.5M/nps. > >No, that is not true. You can get an 100% speedup in NPS without >getting 100% efficiency. This is quite easy, in fact. > >-- >GCP But not on an 8-way using the fusion chipset. the quads scale well due to 4-way memory interleaving. The 8-way still uses 4-way interleaving ahd produces a significant memory bottleneck...
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