Author: Robert Hyatt
Date: 08:23:42 10/29/02
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On October 29, 2002 at 09:18:10, James T. Walker wrote: >It's supposed to mean "double data rate" since the data is supposed to be >transferred on both the leading and trailing edges of the clock cycle. However >it seems to have a negligible effect on chess program performance. Can someone >explain what the problem is and why the hype in the first place? (It's >expensive) >Jim This is just "more of the same" going all the way back to fast page mode, EDO, SDRAM, etc. Latency doesn't change, but bandwidth does. For programs streaming data in/out of memory in contiguous chunks (such as programs that work with large arrays) then the newer tricks work. For programs that do a lot of random addressing, latency is the bottleneck, not bandwidth, and DDR ram actually can hurt as latency went up a bit for DDR as bandwidth went down.
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