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Subject: Re: OT: P4- 3 GHz with hyper-threading

Author: Vincent Diepeveen

Date: 07:01:15 11/03/02

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On November 03, 2002 at 03:29:09, Gian-Carlo Pascutto wrote:

>On November 03, 2002 at 02:00:41, Anthony Cozzie wrote:
>
>>If I understand SMT correctly, its even more than that.  A modern processor has
>>a lot of functional units lying around.  An Athlon can in theory execute 3
>>branches, 3 integer instructions, and 3 floating point instructions every
>>cycle. In reality, most of the time those units are just sitting around. One
>>of the ideas behind SMT is that you can run 2 threads, and split the
>>functional units between them.
>
>The problem with this (and the reason I was surprised SMT works) is that
>it only has 3 decoders and a single cache that is used by both processes.
>
>It is somewhat irrelevant that you have 9 function units if your
>processor is decoder-limited (true for most modern cpus). I guess
>all improvement from SMT is because of memory waiting as Robert
>describes.

1 decoder for P4 even. So if a program is not insane small and if a program
doesn't fit in the 12K trace cache then you are history in advance.

also there is other problems with registers. Just 40 registers to use for
renaming. Too little.



>
>--
>GCP



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