Computer Chess Club Archives


Search

Terms

Messages

Subject: Re: OT: P4- 3 GHz with hyper-threading

Author: Gian-Carlo Pascutto

Date: 07:41:17 11/03/02

Go up one level in this thread


On November 03, 2002 at 10:07:07, Vincent Diepeveen wrote:

>On November 02, 2002 at 00:10:17, Robert Hyatt wrote:
>
>At the P4 with 1 decoder, 12K i cache and just 8KB data cache
>i could measure no speedup. Only slow downs if i tried to run
>too many threads.
>
>Your claims with crafty proofs it fits within the trace cache somehow.

It does almost 10x as much NPS as your thing.

An obvious effect:

It spends (relatively!) much more time waiting for
transposition table entries to come out of main memory

If it spends 20% of it's time for this (a realistic number
on a high end P4) and the parallel speedup is 1.7 then it
is going to run about 5% faster with SMT, roughly.

Crafty doesn't fit in the trace cache - it's bitboards
with not quite compact code. Inferior datastructure and
all that :)

--
GCP



This page took 0.01 seconds to execute

Last modified: Thu, 15 Apr 21 08:11:13 -0700

Current Computer Chess Club Forums at Talkchess. This site by Sean Mintz.