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Subject: Re: OT: P4- 3 GHz with hyper-threading

Author: Gerd Isenberg

Date: 16:24:41 11/05/02

Go up one level in this thread


On November 05, 2002 at 13:36:12, Robert Hyatt wrote:

>On November 05, 2002 at 12:56:34, Gerd Isenberg wrote:
>
>>On November 05, 2002 at 11:26:45, Robert Hyatt wrote:
>>
>>>On November 05, 2002 at 02:43:38, Gerd Isenberg wrote:
>>>
>>>>On November 05, 2002 at 02:01:51, Gian-Carlo Pascutto wrote:
>>>>
>>>>>On November 04, 2002 at 16:35:29, Gerd Isenberg wrote:
>>>>>
>>>>>><snip>
>>>>>>
>>>>>>Gian-Carlo,
>>>>>>
>>>>>>Isn't it necessary to use the lock prefix before xchg?
>>>>>
>>>>>I don't know Gerd. I based this snipped on the locking code
>>>>>in Crafty, and it appears to work fine.
>>>>>
>>>>>--
>>>>>GCP
>>>>
>>>>Aha, then Bob Hyatt may answer this question. The lock prefix makes the
>>>>"xchg"-instruction (read- and write cycle) atomic. So there may be rare cases,
>>>>where two or more processers do the instruction at the same time, both reading
>>>>the semaphore just before the write cycle occurs - and both get zero....
>>>>I thought the lock prefix is exactly for that purpose.
>>>>
>>>>Gerd
>>>
>>>
>>>Good question.  I will do some research.  The spinlock code in crafty came
>>>_directly_
>>>from the linux kernel spinlock.
>>>
>>>OK... From my Intel manual, vol 3 (operating systems):
>>>
>>>The LOCK prefix is automatically assumed for XCHG instruction...  (page 7-4)
>>>
>>>So it seems that the current lock is correct...
>>
>>Thanks Bob, interesting. This XCHG-feature is new to me.
>>
>>Gerd
>
>
>Also seems to imply that using xchg is a bad idea in general, except for atomic
>spinlocks, because the assumed LOCK prefix turns it into a very slow
>instruction.

Yes, but even xchg reg1,reg2 is an expensive vector path instruction on athlons,
blocking all other execution pipes.





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