Author: Robert Hyatt
Date: 19:43:03 11/09/02
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On November 09, 2002 at 07:21:49, Jeremiah Penery wrote: >On November 08, 2002 at 23:59:25, Robert Hyatt wrote: > >>The rename registers are a different issue. They exist within a "logical cpu" >>for optimizing the super-scalar instruction scheduling done by the hardware. >>SMT looks like two distinct cpus, with two distinct _everything_ internal... >>ie two eax registers, one for each thread, two ebx, ecx, edx, esp, flags, >>esi, edi, epb, program counters, etc. IE it _really_ looks like two cpus, >>it just isn't twice as fast as the "pipelines" are really shared internally >>between the two logical cpus, so that only one of those "logical cpus" is >>running at any particular instant. > >The actual microarchitectural (ebx, ecx, etc.) registers are _shared_ resources. I don't understand what that means. IE two threads can not possibly use the same eax register and do anything useful. If you mean that the eax "pointer" (which gets renamed each time it is set to a new value) points to a different rename register in the processor core, that is effectively saying the _same_ thing as each "logical cpu" has its own set of registers. The two _must_ be distinct. > However, the processor has two Register Allocation Tables (RATs), each of which >handles the mapping of architectural registers to a shared pool of 128 GPRs and >128 FPRs (which are basically the rename registers). Every instruction issued >gets a unique rename register destination anyway, always. OK... that is how I thought it worked, which is the same as saying that each logical cpu has its own "eax" register, since each has a unique rename table and no entry in one table can possibly match an entry in the other table. > >Here is a good page that explains some issues: >http://www.arstechnica.com/paedia/h/hyperthreading/hyperthreading-4.html (also >the previous/next pages, but this is the one with the specific info about >register sharing). >It has a table of some things that are shared, partitioned, and replicated >inside a HyperThreaded P4 CPU.
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