Author: Gerard Kopcsay
Date: 20:50:59 11/22/02
Go up one level in this thread
Minus all the PR hype regarding the IBM supercomputer announcement, the two machines described are quite different. ASCII Purple is a direct descendent of the IBM SP line of computers one of which by the addition of the dedicated chess processors became Deep Blue. The main CPU in the SP used in Deep Blue 2 was based on the PowerPC-2 architecture and ran at 120-135 MHz. An SP node consisted of a single CPU along with its memory, disks, etc. The ASCII White supercomputer (which is #4 on the current top 500 supercomputer list, and was delivered to LLNL in 2000) is a 512 node SP. Each node consists of a 16-way SMP using PowerPC-3 processors running at 375 MHz. The IBM PR folks claimed that ASCII white was 1000X the performance of DB2. This claim seems to be based on simply multiplying the ratio of the number of processors in the two machines by the increase in processor performance, and completely ignores the chess processors that were the heart of DB. The separate nodes in an SP machine are connected via a network, and communicate by exchanging messages or packets (i.e. a loosly coupled or "message passing" architecture). As Bob Hyatt has pointed out, it is not clear how to scale even the parallel search used in DB up to such a large, loosely coupled system. ASCII Purple will have up to 196 nodes, where each node is a 64-way SMP using a PowerPC-5 2 way processor chip. I don't know the exact speed, but the chip is to be an upgraded version of the PowerPC-4 2 way processor chip used in the current IBM p690 e-server, a 32W SMP, which runs at 1.3 GHz. ASCII Purple's advertised peak performance of 100 TFlops is roughly 10X that of ASCII White. So this obviously makes it 10,000X faster than DB. :-) Blue Gene/L is, however, completely different. The basic system concept was described in a paper presented at ISSCC in Feb 2002. (An update has been accepted for the next ISSCC in Feb. 2003.) Blue Gene/L will use a system on a chip (SOC) ASIC that contains 2 PowerPC processor cores, embedded DRAM memory, a memory controller to interface with external DDR SDRAM, and multiple high speed serial link interfaces for node to node communication. The compute ASIC was described at the recent IEEE Clustered Computing Conference. A BG/L system consists of up to 64K nodes, interconnected by multiple networks including a 3D torus (direct nearest neighbor communication), and a global tree (for broadcast to all nodes). It is to be packaged with 1024 nodes per frame (compared to 4 nodes or 64 processors per frame for ASCII White). To achieve this density requires low processor power (around 10 W), so the processor speed will likely be under 1 GHz. Whenever you use tens of thousands of any component, its cost and power consumption are critical. Again, these nodes are loosely coupled, and communicate via packets transmitted on the links. A huge effort has been made to reduce the link latency compared to the SP class machines, but the node to node separations can be large, and so are the delays. Thus link latency will still be many times larger than local memory latency. An additional ASIC design is used to implement the high speed network links. These ASICs redrive signals over the cables that connect nodes in different frames, and also enable partitioning of the machine. The first hardware for this link ASIC has recently been fabricated, and the chip is now running in my lab at an aggregate data rate of over 100 Gbit/s (up to 2 Gb/s per link). I will not even guess at what performance factor the PR folks will claim for BG/L compared to Deep Blue. However, I expect it would require a major effort to write a parallel search that has any chance of running efficiently on such a massively parallel computer. Complex software issues must be resolved to effectively utilize BG/L even for the numerically intensive scientific computing problems for which it was designed. And, of course, IBM no longer has any incentive to develop a new chess program. :-)
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