Author: Robert Hyatt
Date: 09:01:19 12/06/02
Go up one level in this thread
On December 05, 2002 at 08:24:08, Jeremiah Penery wrote: >On December 05, 2002 at 06:31:27, Matt Taylor wrote: > >>On December 04, 2002 at 21:58:27, Jeremiah Penery wrote: >> >>>Current AthlonMP chipsets also have a seperate bus per CPU. They use the same >>>EV6 bus as Alpha processors did (or still do?). The memory modules shared, >>>whereas Hammer will have separate memory modules for each processor. >> >>Yes and no. Each CPU has a dedicated bus to the memory controller (and to any >>other CPU??). However, there is only one memory bus (bus that physically >>connects to the memory chips), and that bus is shared by all processors. Intel > >Yep. > >>has the same limitation, but Intel uses other tricks to further double the >>memory bandwidth (and effectively make memory access no more costly on SMP than >>on single-CPU). Unfortunately, AMD has not. (The AMD 760 and 760 MPX are the >>only Socket A SMP chipsets available, and neither has this capability.) > >Intel SMP machines have only one bus to the memory controller, that is shared by >all processors. That is the difference I was trying to point out, but couldn't >quite say properly last night. :) True. Fortunately they are using 2-way interleaving (for duals) or 4-way interleaving (for quads) to double or quadruple the memory bandwidth and prevent bad starvation problems. Not all duals do interleaving however, and those that don't show a marked degradation in performance when running a memory-intensive application...
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