Author: Robert Hyatt
Date: 14:46:03 12/09/02
Go up one level in this thread
On December 09, 2002 at 17:26:07, Dieter Buerssner wrote:
>On December 09, 2002 at 17:15:12, Robert Hyatt wrote:
>
>
>>void __inline__ LockX86(volatile int * lock) {
>> int dummy;
>> asm __volatile__ (
>> "1: movl $1, %0" "\n\t"
>> " xchgl (%1), %0" "\n\t"
>> " test %0, %0" "\n\t"
>> " jz 3f" "\n\t"
>> "2: pause" "\n\t"
>> " movl (%1), %0" "\n\t"
>> " test %0, %0" "\n\t"
>> " jz 2b" "\n\t"
>> " jmp 1b" "\n\t"
>> "3:" "\n\t"
>> : "=&r" (dummy)
>> : "r" (lock)
>> : "cc");
>: "cc", "memory");
>>}
>>
>>I tried changing the "r" to "q" to limit the register choices in case esi/edi
>>won't work
>>in some of the above, but I don't see anything wrong. If I remove the
>>__inline__ then it
>>seems to work just fine. With the inline in, it breaks things in unpredictable
>>ways...
>>
>>Anything obvious (or not-so-obvious) that jumps out at you?
>
>I don't know much about locks. Have you tried to give the lock prefix in front
>of the xchgl? To me it looks, like any register should do, so I agree with "r"
>(and "q" seems unneeded).
>
>I never tried "=&r". I allways used "=r&" when the "&" was needed. However I
>cannot remember, if this is needed. Another formal error, is that you don't tell
>the compiler, that you change memory. However, I don't know, if he actually uses
>this info. See the line above in the code.
>
>I would use testl instead of test, but I think, it won't make a difference.
>
>Regards,
>Dieter
According to the intel docs, the xchg instruction is a interlocked instruction
already,
and the lock prefix is redundant. My current lock code does not have this and
it works
fine, so there is more than that going on.
As far as memory, the only two things that use the locks are the Lock() and
Unlock()
asm codes so I don't think it matters. Also all locks are declared volatile and
can't be
held in registers for optimizing anyway...
I will keep looking as something is fishy...
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