Author: Matt Taylor
Date: 16:09:25 12/09/02
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On December 09, 2002 at 18:44:14, Dieter Buerssner wrote: >On December 09, 2002 at 17:46:03, Robert Hyatt wrote: > >>According to the intel docs, the xchg instruction is a interlocked instruction >>already, >>and the lock prefix is redundant. My current lock code does not have this and >>it works >>fine, so there is more than that going on. > >Thanks for pointing this out (also, to Matt) Is the implicit lock perhaps >dependent on the actual register used, or is it independent of the register= xchg has implicit locking semantics regardless of operands. I believe bts (bit test and set) does as well, but don't quote me on that. -Matt
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