Author: Matt Taylor
Date: 02:08:25 12/17/02
Go up one level in this thread
On December 17, 2002 at 03:58:32, Gerd Isenberg wrote: >On December 17, 2002 at 01:47:27, Walter Faxon wrote: > >>On December 16, 2002 at 15:05:56, Gerd Isenberg wrote: >> >>>Hi all, >>> >>>My conclusion with Athlons bit scan (and reset) routines so far: >>> >>>Inlined bsf is the fastest for IsiChess, because of shortest code! >>> >>>Walter Faxon's magic LSB_64 and bitSearchAndReset_MMX (both faster not inlined) >>>both produce a about 3-5% slower IsiChess. LSB_64 and bitSearchAndReset_MMX are >>>equal in IsiChess. In a dumb-loop test bitSearchAndReset_MMX is clearly the >>>fastest (14.9 seconds) for 10^8 * 10 bits resets. >>> >><snip> >> >> >>It's understandable that even if bsf itself is relatively slow, its not needing >>so many registers to do its work may more than make up the difference. >> >>Still, I'm confused. If the other two routines are not inlined, there must be >>at least a little procedure call overhead, right? The registers they need will >>have to be saved/restored either way. How can _not_ inlining produce faster >>code? Matt, help! >> >>-- Walter > >Hi Walter, > >it depends on the program of course. In IsiChess inlined LSB_64 is definitely >slower than _not_ inlined. Even code must be read into L1-cache, and more code >implies more memory reads - there are so many "chaoic" interferences, at least >in IsiChess, but i guess also in other programs. > >Cheers, >Gerd Shouldn't be a big issue, though. They aggressively speculatively fetch code into the L1 cache, and the cache is huge. AMD advises in all the optimization guides to "aggressively unroll loops [because of large cache size]." The register contention seems more likely IMO... -Matt
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