Author: Vincent Diepeveen
Date: 19:33:03 12/31/02
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On December 30, 2002 at 23:18:31, Matt Taylor wrote: >On December 30, 2002 at 19:32:57, Dan Andersson wrote: > >>http://www.digit-life.com/articles2/amd-hammer-family/index.html >>The memory part is interesting. If it works out in practice it will be fast >>miltiprocessing. >> >>MvH Dan Andersson > >Most of the facts were grossly wrong, but yes, the memory system implemented on >x86-64 chips is very interesting. > >I struggle to believe that they have achieved 55-ns access times. My system is It is not impossible 55ns access times. Router latency at the TERAS supercomputer is 50 ns for each router. Actually they assume way faster than 55ns access times. >based around the 760MPX chipset and uses Registered/ECC ram, and my access time >is about 133 ns (not the 200 ns the article claims). By integrating the memory I didn't measure accurate but are we speaking here about random accesses or not sequential accesses. How many system clocks does that translate to for a 2Ghz K7 MP for a random lookup in memory which is not in L2 and also not in an opened memory line? >controller, they probably achieve access times of ~90-100 ns. The biggest >latency here is the memory itself, not the controller. > >Four-way systems have been built and demonstrated by AMD. AMD is keeping the >performance figures hush-hush, but the one thing they have said is that an >eight-way system will have no more latency worst-case than existing >single-processor systems. With an OS that understands the architecture, you'll >get better performance. >-Matt please write down this 8 way promise. They did the same about K7 some years ago. But it was very vague words which everyone seems to be forgotten now.
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