Author: Matt Taylor
Date: 22:27:03 12/31/02
Go up one level in this thread
On December 31, 2002 at 22:33:03, Vincent Diepeveen wrote: >On December 30, 2002 at 23:18:31, Matt Taylor wrote: > >>On December 30, 2002 at 19:32:57, Dan Andersson wrote: >> >>>http://www.digit-life.com/articles2/amd-hammer-family/index.html >>>The memory part is interesting. If it works out in practice it will be fast >>>miltiprocessing. >>> >>>MvH Dan Andersson >> >>Most of the facts were grossly wrong, but yes, the memory system implemented on >>x86-64 chips is very interesting. >> >>I struggle to believe that they have achieved 55-ns access times. My system is > >It is not impossible 55ns access times. Router latency at the TERAS >supercomputer is 50 ns for each router. > >Actually they assume way faster than 55ns access times. Not impossible to achieve 55 ns, but considering we are still talking about DRAM and PC architecture, I have difficulty believing that the latency is that low. It has always been my understanding that the major latency came from the DRAM itself, not the chipset. The latency of Hypertransport is something like 2 bus clocks (I think??), and the minimum speed is 200 MHz (5 ns/clock). Assuming 3 hops (8-way SMP) and 2 clocks latency, this is 5*2*3=30 ns latency. This is why I don't think AMD will get any better than 80-90 ns, at least with Registered/ECC ram -- the implication was that the worst-case in 8-way SMP is about equal to normal latency. >>based around the 760MPX chipset and uses Registered/ECC ram, and my access time >>is about 133 ns (not the 200 ns the article claims). By integrating the memory > >I didn't measure accurate but are we speaking here about random accesses >or not sequential accesses. > >How many system clocks does that translate to for a 2Ghz K7 MP for >a random lookup in memory which is not in L2 and also not in an opened >memory line? An AthlonMP 2000 (1.67 GHz) or an AthlonMP 2400 (2.0 GHz)? This is 133-ns for random memory access on Registered/ECC DDR SDRAM (CL 2.5 133 MHz pc2100). For the AthlonMP 2400 (2.0 GHz), each clock is 0.5 ns. 133/0.5 = 266 clocks memory latency worst-case. >>controller, they probably achieve access times of ~90-100 ns. The biggest >>latency here is the memory itself, not the controller. >> >>Four-way systems have been built and demonstrated by AMD. AMD is keeping the >>performance figures hush-hush, but the one thing they have said is that an >>eight-way system will have no more latency worst-case than existing >>single-processor systems. With an OS that understands the architecture, you'll >>get better performance. >>-Matt > >please write down this 8 way promise. They did the same about K7 some >years ago. But it was very vague words which everyone seems to be >forgotten now. AMD lists in their processor roadmap that they intend to do 8-way SMP, and they've packaged the Opteron with 3 Hypertransport links instead of 2. I haven't looked for any sort of public statement about such systems. 4-way systems have been demonstrated by AMD already and are a reality. They still claim 8-way, by the way: http://www.amd.com/us-en/Processors/ProductInformation/0,,30_118_608,00.html -Matt
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