Author: Gerd Isenberg
Date: 12:59:57 01/10/03
Go up one level in this thread
Hi Uri,
if you have an athlon, msc6 and processor pack installed, try this one from
amd's optimization manual:
Regards,
Gerd
//--------------------------------------------------------------------------
#ifdef ATHLON_MMX
#include <amd3dx.h>
struct SBitCountConsts
{
BitBoard C33;
BitBoard C55;
BitBoard C0F;
...
};
extern const SBitCountConsts BitCountConsts;
#pragma warning(disable:4035) // no return value
__forceinline
int PopCount (BitBoard bb)
{
__asm
{
movd mm0, word ptr bb
punpckldq mm0, word ptr bb + 4
lea eax, [BitCountConsts]
movq mm1,mm0
psrld mm0,1
pand mm0,[eax].C55
psubd mm1,mm0
movq mm0,mm1
psrld mm1,2
pand mm0,[eax].C33
pand mm1,[eax].C33
paddd mm0,mm1
movq mm1,mm0
psrld mm0,4
paddd mm0,mm1
pand mm0,[eax].C0F
pxor mm1,mm1
psadbw mm0,mm1
movd eax,mm0
}
}
#pragma warning(default:4035)
...
This page took 0 seconds to execute
Last modified: Thu, 15 Apr 21 08:11:13 -0700
Current Computer Chess Club Forums at Talkchess. This site by Sean Mintz.