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Subject: Re: you guys are missing one of the biggest problem with IA64

Author: Matt Taylor

Date: 23:21:38 02/11/03

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On February 12, 2003 at 00:27:20, Anthony Cozzie wrote:

>and it is called a Cache Miss :) There is no way for a compiler to account for
>cache misses.
>
>it's one of the big problems with Itanium: get a cache miss, and the whole thing
>grinds to a halt.
>
>anthony

That is a problem on every architecture. A lower clock speed actually helps in a
way -- fewer cycles get wasted, so a lower percentage of the machine's power is
wasted idling. McKinley runs at 1 GHz meaning that 1 cycle = 1 ns. Typical
latency for SDRAM seems to be 100-133 ns. RDRAM is worse, but I don't have
figures for RDRAM. (IIRC, McKinley only runs on RDRAM.)

-Matt

• Re: you guys are missing one of the biggest problem with IA64 Tom Kerrigan 01:57:35 02/12/03
  • Re: you guys are missing one of the biggest problem with IA64 Robert Hyatt 08:39:04 02/12/03
    • Re: you guys are missing one of the biggest problem with IA64 Tom Kerrigan 13:06:43 02/12/03
      • Re: you guys are missing one of the biggest problem with IA64 Robert Hyatt 18:01:01 02/12/03
    • Re: you guys are missing one of the biggest problem with IA64 Matt Taylor 11:57:13 02/12/03

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