Author: Matt Taylor
Date: 20:20:52 02/12/03
Go up one level in this thread
On February 12, 2003 at 04:45:42, Tom Kerrigan wrote: >On February 12, 2003 at 01:58:36, Matt Taylor wrote: > >>Branch prediction is mostly unrelated to OOOE. The IA-64 does have branch >>prediction. It does not have OOOE. > >Of course it's related. Compilers have to rely on static branch prediction (80% >accuracy) if they're going to effectively advance instructions before branches. 80% accuracy when you do it at runtime. The compiler can know the -exact- probabilities of each branch and take advantage of this. The compiler can know with near-100% certainty where most branches will go. The only variable is input, and every combination of input is assumed to have equal probability. >>On a final note, the Athlon has a 72-entry integer scheduler and IIRC a 36-entry >>FP scheduler. Athlon can therefore see up to 72 instructions ahead. (Remember -- >>1 DirectPath instruction translates 1:1 with a macro-op, or this is the >>impression I get from the docs anyway.) The compiler can still see futher. > >Indeed. It's a shame only IA-64 chips run compiled code... oh, wait... I'm sure I tried to claim that IA-64 is the only chip that runs compiled code. Most IA-32 compilers do not attempt branch prediction. The Intel C compiler does some; to what extent I do not know. I can't comment on the state of the IA-64 compilers. >>No. Predication is the IA-64's answer to branch prediction. Predication is >>completely unrelated to OOOE. > >What, exactly, do you think the point of predication is, then? It's to allow >instructions to execute before the condition is determined, in other words, out >of order. (Or at least in order without being dependent.) If you think >predicated instructions are only executed after the condition is determined, >then what is the difference between a "predicated branch" and a normal branch, >besides some extra instructions? Predication avoids small conditional branches such as the infamous abs, max, and min functions. >>Dr. Hyatt's figures "in practice" still show an 1 GHz McKinley 4 times faster >>clock-for-clock than a Pentium 4. > >And every other SPEC program shows that "in practice" McKinley is clearly slower >than a P4. So there are two results, and you prefer to throw away one rather than attempting an explanation. >>The last two questions are more an answer to the question, "How will the IA-64 >>scale?" The question I am answering (and the question originally asked) is, "How >>fast currently is the IA-64 compared to the IA-32/AA-64 in Chess?" > >Your confusion about the original question continues. Somebody asked what the >relative advantages of x86-64 and IA-64 are. It had nothing to do with IA-32. I >have no way to prove this because the post seems to be gone, but I also >distinctly remember writing a post with lists of advantages for each chip and >not mentioning anything about IA-32. It has everything to do with IA-32. IA-32 is a standard to measure up against. Furthermore, x86-64 has its history in IA-32. I believe IA-32 is perfectly relevant even if only for explaining what advantages x86-64 will have. >As for all the extraneous trivia you provided about the chips in question, don't >bother. I already know it. I post trivia in response to specific questions. Most of the time it is not for your sake. The title of this forum is "Computer Chess Club", not "Computer Engineering Consortium." -Matt
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