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Subject: Re: IA-64 vs OOOE (attn Taylor, Hyatt)

Author: Matt Taylor

Date: 22:56:11 02/12/03

Go up one level in this thread


On February 12, 2003 at 21:07:57, Robert Hyatt wrote:

>On February 12, 2003 at 16:13:29, Tom Kerrigan wrote:
>
>>On February 12, 2003 at 11:47:21, Robert Hyatt wrote:
>>
>>>But I don't
>>>think OOOE is _nearly_ as important for decent architectures as it is for
>>>architectures
>>>that have significant design problems like X86.
>>
>>Fine, it's a 30% benefit to Alpha and MIPS, maybe it's 40% for x86...
>>
>>>>>The Cray T932 was the last 64 bit machine they built that I used.  And it
>>>>How many NPS does Crafty get on it?
>>>about 7M.
>>>And that was Cray Blitz, not Crafty.  I have not tried to run Crafty on a Cray,
>>
>>7M per processor? How many processors did those Crays come with? 32? So Crazy
>>Blitz was searching 224M NPS? I stand corrected, the T932 is several times
>>faster than any other processor ever made.
>
>No.  7M total as I said, spread over 32 processors (actually we only used 31
>on that machine so that one could be dedicated to handling interrupts and the
>like to avoid unnecessary context switches).
>
>>
>>>>>I did a branchless FirstOne() in asm a few weeks back here, just to test.
>>>>>It used a cmov, and it wasn't slower than the one with a branch.  If the
>>>>On a Pentium III?
>>>On a pentium IV.
>>>Although I did test it on my PIII xeon box, so I guess the answer is "yes" to
>>>the III as
>>>well...
>>
>>You "guess"? I never said anything about cmovs being bad for the P4, so why do
>>you keep talking about the P4?
>>
>>-Tom
>
>I ran it on both, as I said.  I simply almost forgot that my 700's were PIII's
>while my dual 2.8 is PIV's.  I did the testing on both since I use both to
>play chess and fiddle with assembly.
>
>Restated:  I ran the branchless stuff on a PIII/700 xeon, and a PIV/2800 xeon.
>It worked well on both.  I "guess" it therefore works well on all PIII/PIV
>processors, even though I only have xeons to test.

The only difference is the cache -- Xeons have more cache than the desktop
chips. (Plus Xeons support 36-bit addressing in the cache. I have been told that
the desktop varieties do not.)

-Matt



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