Author: Tom Kerrigan
Date: 10:20:38 02/18/03
Go up one level in this thread
On February 16, 2003 at 00:04:34, Eugene Nalimov wrote: >On February 15, 2003 at 21:37:19, Tom Kerrigan wrote: > >>On February 13, 2003 at 15:46:26, Eugene Nalimov wrote: >> >>>Some time ago I wrote in the (lost) thread: please compare Itanium2 not with >>>P4/Athlon/etc., but with server CPUs. I.e. with 4-way Xeons, Power4, etc. >> >>I don't know how I got dragged into talking about x86 at all. Everybody seems to >>assume that I want to prove that the P4 is better than the I2 in all cases no >>matter what. The comparison I'm interested in is Opteron vs. I2... >> >>>benchmarks it resembles real-world server-like code a most: it's (relatively) >>>large, execution time not spent in several functions but heavily spread across >>>lot of functions, lot of loops across pointer chains, lot of calls, >>>unpredictable branches, etc. >> >>In other words, it's suited to chips with lots of cache or low latency memory >>and low branch mispredict penalties. Opteron addresses all of these issues. > >Why it should be better than Power4+? Higher clock speeds (if not initially, shortly thereafter) and lower branch mispredict penalties. (12 vs 17 stage pipeline.) Also, is the POWER4's memory controller on-die or just in-package? If it's not on-die, that's a big memory latency advantage for x86-64... -Tom
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