Author: Tom Kerrigan
Date: 15:06:43 02/19/03
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On February 18, 2003 at 13:45:49, Eugene Nalimov wrote: >(1) Why x86-64 should has higher clock speed? 1,450MHz Power4+ is shipping for >several months already. The only possibility I see is that IBM will not clock >Power4+ aggressively, mainly because RAS for server CPUs is more important than >pure speed. But than I doubt that AMD would clock server version of x86-64 >aggressively, too. The Hammer core is pretty much the same as the Athlon core but with a couple more pipeline stages, so as soon as AMD works out its issues with SOI, Hammer should clock higher than current Athlons. Opterons will be released at up to 1.6GHz (in ~April?) anyway, which is already faster than the POWER4+. >(2) You yourself wrote "lots of cache or low latency memory". Power4+ has so >much cache that I believe it would more than compensate faster x86-64 memory >latency. I guess we'll have to wait and see. :) >Returning to the original point: I still don't see why x86-64 should be better >than Power4+, and on the server-like code current Itanium2 is faster (and, BTW, >cheaper) than higher clocked Power4+. So probably for such code in-order >execution is not much worse than OoO (as you suggested)? Or probably not worse >at all? The I2 and POWER4 are very different even ignoring how they issue instructions. Pipeline lengths, memory heierarchies, etc. Actually, the POWER4 issues bundles of 5 instructions, so it's sort of VLIW also. Its performance would definitely be better with more issue granularity, but this isn't really a handicap vs. the Athlon/Hammer, as the latter also issues macro-ops. -Tom
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