Computer Chess Club Archives


Search

Terms

Messages

Subject: Re: Introducing "No-Moore's Law"

Author: Robert Hyatt

Date: 20:38:21 02/28/03

Go up one level in this thread


On February 28, 2003 at 18:36:32, Tom Kerrigan wrote:

>On February 28, 2003 at 11:45:18, Robert Hyatt wrote:
>
>>Actually it isn't.  Silicon compilers do a lot of the work I had to do by hand.
>>Summing
>>gate delays.  Doing the routing.  And in my day, an error was a terrific delay
>>as it took a lot
>>of time to re-do.  With silicon design tools, that process is much simpler from
>>the human's
>>perspective today, which is a plus.
>
>If, by silicon compilers, you mean HDL tools, they aren't used much in high
>performance microprocessor design.
>
>Some recent Intel slides on Prescott indicate they're using cool new routing
>automation tools, though.
>
>-Tom

The routing automation was the main point.  It is a horribly expensive (in
terms of computational complexity) thing to do, that saves the engineers a lot
of time.  Very similar to CAD systems used by architects to create and modify
blueprints.  They off-load the things that can be computed (such as new
ceiling heights change stairway lengths, door locations, etc) to the computer
making it easy for the designer to fiddle with the thing without having to spend
days re-drawing.




This page took 0.01 seconds to execute

Last modified: Thu, 07 Jul 11 08:48:38 -0700

Current Computer Chess Club Forums at Talkchess. This site by Sean Mintz.