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Subject: So why does Itanic get faster w/ more cache?

Author: Tom Kerrigan

Date: 17:33:46 03/18/03

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Interesting case of seemingly conflicting data...

Maybe by turning off half the chip's cache, it decreased the associativity
enough to cause contention for some critical data. That's the best explanation I
can think of.

Nice benchmarking, Aaron. :)

-Tom



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