Author: Robert Hyatt
Date: 20:32:42 03/19/03
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On March 19, 2003 at 22:50:43, Tom Kerrigan wrote: >On March 18, 2003 at 23:09:08, Robert Hyatt wrote: > >>Yes you are. You have the fastest single CPU on the planet. Notice that to > >Uh, my CPU? > >>>If you have a 133MHz DIMM that's rated at 2-1-1-1, it can obviously access a >>>word in 15ns. >>I don't believe 15ns for a second. Just look at current specs for DRAM and >>tell me how that is going to happen? Again, look at any memory benchmarking > >Instead of telling me to "run the test" or "look at the current specs for DRAM," >why don't you just tell me what's wrong with my reasoning? I'm explaining >exactly how I'm getting my numbers, so it should be easy for you (the computer >architecture professor) to tell me what's wrong. When you're teaching DRAMs in >your comp arch class, do you just stand at the board and say "run the test" and >"look at the specs"? > >-Tom Nope. But when I cover such a topic, I have hardware close by to demonstrate what is going on. I don't believe in a random access probe into a DRAM chip that can happen in 15 ns, at least not in any DRAM chip I have seen advertised by any DRAM maker. You can get to that kind of _average_ latency if you assume consecutive addresses so that the original random (long) latency gets amortized over several following consecutive reads. But latency is defined as the time to do a random read, which is what we have been talking about. The time needed to access successive words is certainly important on the PIV with 128 byte L2 cache lines, but it doesn't affect the time to access the first word at a random access... As to pointing out where your error is, I can only point to the 15ns as not being realistic. I have no idea what kinds of other delays you might experience since I don't have your hardware. But lmbench will certainly give you a correct latency number that compares to numbers produced by others on various platforms. I've run it on all kinds of things over the years... And the other data it gives makes it worth the time, as it is interesting to see how all parts of a particular machine perform, in the real world as opposed to "on paper". By the way, when I talk about DRAM in class, the problems are made pretty obvious as to the random latency and then sequential latency, with a discussion about resistance, capacitance, and inductance issues that make DRAM a pain. At least when compared to SRAM.
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