Author: Matt Taylor
Date: 23:42:54 03/19/03
Go up one level in this thread
On March 19, 2003 at 22:47:51, Tom Kerrigan wrote: >On March 18, 2003 at 20:49:24, Matt Taylor wrote: > >>On March 18, 2003 at 19:45:43, Tom Kerrigan wrote: >> >>>On March 18, 2003 at 18:20:14, Robert Hyatt wrote: >>> >>>>On March 18, 2003 at 17:46:10, Tom Kerrigan wrote: >>>> >>>>>On March 18, 2003 at 16:37:35, Robert Hyatt wrote: >>>>> >>>>>>>>1. no interleaving, which means that the raw memory latency is stuck at >>>>>>>>120+ns and stays there. Faster bus means nothing without interleaving, >>>>>>>>if latency is the problem. >>>>>>> >>>>>>>Uh, wait a minute, didn't you just write a condescending post to me about how >>>>>>>increasing bandwidth improves latency? (Which I disagree with...) You can't have >>>>>>>it both ways. >>>>>>> >>>>>>>Faster bus speed improves both latency and bandwidth. How can it not? >>>>>> >>>>>>It doesn't affect random latency whatsoever. It does affect the time taken to >>>>>>load a >>>>>>cache line. Which does affect latency in a different way. However, >>>>>>interleaving does >>>>>>even better as even though it doesn't change latency either, it will load a >>>>>>cache line even >>>>>>faster. >>>>> >>>>>Are you kidding me? How can FSB speed _not_ affect latency? >>>> >>>>Very simple. Latency is caused _in_ the memory system, only a tiny part of >>>>latency >>>>is caused by the delay of shipping the data over the bus. If you ran the bus >>>... >>>>Run the test. This discussion was held on r.g.c.p a while back. And the _same_ >>>>results were found. Memory has 120ns latency no matter _what_ memory you >>>>use. RDRAM is even slower in terms of latency. If you can get your memory to >>>>sub-100ns latency, you've done a miracle in modern electronics. >>> >>>I guess I'm sitting in front of one miraculous computer, then, because it can >>>randomly access a word in 75ns. Just ran the test. (RDRAM, BTW.) >>> >>>If you have a 133MHz DIMM that's rated at 2-1-1-1, it can obviously access a >>>word in 15ns. If the system gets that word in 75ns (ignoring RDRAM vs. DIMM >>>latency for now) that means 20% of the latency is from the memory and 80% (not >>>"a tiny part") is from "shipping the data over the bus" (and through the >>>northbridge). Conventional wisdom says there's a 10ns wire/pin delay for a >>>signal going into or out of a chip, so into northbridge + out of northbridge + >>>into processor = 30ns. That means 30ns of processing is done on the northbridge >>>and processor. That's why everybody is so worked up about Hammer's on-die memory >>>controller--it reduces memory latency by, well, somewhere between 20 and 50ns, >>>or roughly 50%. >>> >>>End of today's lecture... >>> >>>-Tom >> >>What happened to the RAS timings? The latency of DDR on my SMP machine is about >>133 ns random access. I think this is about 100 ns random access on a standard >>CL 2.5 pc2100 DDR system. Using CL 2 cuts off a few nanoseconds, but not a whole >>lot. > >I'm not sure what CAS2 or the leading 2 of 2-1-1-1 means. I looked up the timing >digrams for paged DRAMs in some of my textbooks at home and it's not clear if >they mean CAS is low for 2 cycles, or what. I know that the -1-1-1 part means >that the last three words of the burst are on consecutive cycles, so I've always >assumed the leading 2 is the latency (in cycles) for accessing a, i.e., any, >word. > >This was backed up by a discussion a while back on Ace's Hardware where Paul >DeMone (who designs DRAM for a living, IIRC) stating that random access times >for PCsomething are ~20ns... The latency of a memory access on Clawhammer is at -least- 40 ns (the lowest figure I have seen reported). I saw another figure of 70-80 ns. I am not sure which one is correct. On my dual-Athlon, I get 133 ns per Sciencemark. Here are timings I obtained for an nForce 2 board: http://www.talkchess.com/forums/1/message.html?290002 I do not doubt that better can be obtained. Aaron got as low as 68 ns with a 220 MHz bus and fast ram. I did a quick google search and turned up this webpage: http://www.sysopt.com/articles/latency/ Their explanation is fairly simple, and it reiterates what Bob and I have been saying. You add RAS, RCD, and CAS to get the latency for a random access. For my synchronous result (166 MHz memory bus) my latency was about 118 ns. RAS+RCD+CAS=12.5 clocks or 75 ns, so 43 ns came from the chipset & CPU. Perhaps tomorrow I'll change the FSB speed and run synchronous tests at varying speeds. I have a pc2700 module which I would like to test, but unfortunately the board rejects it even at 100 MHz. (Other boards run it fine at 133 MHz.) If I can get working pc2700 memory, I will test it at full blast and post more latency figures for "bleeding edge" stuff. >>Also, ramping the memory bus speed doesn't change latency very much. Most chips >>report a different CAS latency depending on the FSB speed. I have a DIMM rated >>CL 2.5 133 MHz (pc2100). When I use SPD detection and clock it at 100 MHz, it >>reports itself as CL 2. At 133 MHz this is 19 ns. At 100 MHz this is 20 ns. It's >>approximately equal. > >Well, yes, when talking about varying the FSB, I thought it was understood that >nothing else in the system would vary, i.e., the memory timings. Sure, if you want to make an unreasonable assumption. Timings -always- change when you change the FSB. As I pointed out, the SPD on that specific pc2100 DIMM works to keep the latency just above the rating at any FSB speed. The first pc2700 parts were pc2100 parts with adjusted latency figures (i.e. CL 2 -> CL 2.5). For a while, pc2700 with CL 2 was not even available. Clocking the ram higher does not necessarily mean the latency is any different. -Matt
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