Author: Robert Hyatt
Date: 09:40:45 04/04/03
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On April 04, 2003 at 01:51:53, Jay Urbanski wrote: >On April 03, 2003 at 23:13:14, Robert Hyatt wrote: > >>But only the duals. My quad xeon gets nearly 2.0 speedup with 2 threads. >> >>Something is fishy. I'm looking at the new longer cache line stuff to see >>if I have some things I can move around to prevent contention. > >Yes, but your quad is a Pentium III Xeon. The new "Xeons" are all based on the >Pentium 4 core; those are the only ones so far that seem to exhibit this >problem. (has anyone tried AMD?) I would hazard a guess that a 4-way P4 Xeon >would exhibit the same problem; unless a larger cache masks the problem. I have been carefully looking at the differences, and the only thing I see so far that seems even remotely related is the 128 byte L2 line length. If two processrs are fiddling with data in the same 128 byte line, then cache invalidates can be a big problem. I'm looking at the code to try to see what might be going on, but so far that is the only possible explanation and it looks _really_ remote to me at the moment. Eugene also mentioned alignment and I'm studying that as well... But you are correct, this seems to be a PIV issue, and I don't have any PIV quads around. If someone does, please let me know and we can try the same test to see if the problem is PIV-based or quad-vs-dual based...
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