Author: Marc Boulé
Date: 12:13:44 04/10/03
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>Hey Marc, > >I hadn't done anything because I didn't want to shell out for a board, and I was >pretty busy working on a chip. > >But a friend just gave me a couple of development boards, plus this stuff at >work became available after our chip architecture grew and we had to stuff some >new boards with bigger FPGAs, thus making the older ones obsolete. > >Maybe I should synthesize your movegen as-is and see how well it fits into a >XC2V4000 part. I think that you used XCV800 in your work right? So we have a >40/8 = 5X increase in gates by the part numbers alone, plus additional Virtex II >features which should help improve routing... > >I have to tell you that I work only in Verilog, so I would create a new move >generator in Verilog eventually :-) > >Keith Yes, it was an XCV800. The diagonal routing in VirtexII should be very helpful for interconnecting chess squares diagonaly. In any case (VHDL or Verilog) it would be best to re-code it because you would learn alot and perhaps do a better job than me :-). Plus you would implicitly know how to interface it to the rest of the chess system, a task not so easy if you use someone else's design. Man, you have some big FPGAs! 6x XC2V4000 ! You could pack a hell of a positional evaluator in that! Not to mention the move gen and search control. I should be getting my VirtexII-Pro soon, i'll let you know how it goes... Marc
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