Author: Anthony Cozzie
Date: 14:03:00 04/17/03
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I ask because 1) mmx instructions have a 2-cycle latency on the athlon, 2) getting the data over to the MMX pipe and back takes at *least* 6 cycles 3) this is not really a 64 bit operation 4) I tried AMDs 'optimized' version and it turned out to be much slower than the simple C hack I'd be very interested in any performance numbers you have. anthony
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