Author: Tom Kerrigan
Date: 11:36:37 04/21/03
Go up one level in this thread
On April 21, 2003 at 10:05:15, Aaron Gordon wrote: >On April 21, 2003 at 07:19:50, Tom Kerrigan wrote: > >>On April 21, 2003 at 05:05:08, Aaron Gordon wrote: >> >>>The same way a Celeron 1GHz, P3-933MHz or 900MHz Athlon is faster than a Pentium >>>4 1.5GHz. MHz isn't everything. Pentium 4's were made with only 1 thing in mind, >>>marketing. Make a chip with high MHz so people will think it's faster. To get >>>those high MHz numbers they had to gimp the CPU, which is why the Pentium 4's >>>are ridiculously slow MHz for MHz. >>> >>>In some applications it has the IPC (instructions per cycle) of a 486. I don't >>>know about you, but I upgraded from a 486 a long time ago.. :) >> >>What part of the P4 is gimped? >> >>According to SPECint, >> >>http://www.aceshardware.com/SPECmine/index.jsp?b=0&s=2&v=2&if=0&r1f=2&r2f=0&m1f=0&m2f=0&o=0&o=1 >> >>AXP only has 15% more IPC than a P4. Also notice that the AXP has dramatically >>lower IPC than MIPSs, PA-RISCs, POWERs, and Alphas. Surely you will argue that >>AMD sacrificed IPC for clock speed for a net gain in performance. Perfectly >>legitimate argument, and the same argument one could make for the P4. > >Well, when you start needing P4's running nearly 6GHz to equal my AthlonXP >2.5GHz in some things, you have to admit they screwed that chip pretty bad. >Lots of stuff like rendering, simulations, etc, all run slow. Not really. Processors have their strengths and weaknesses. I'm sure you could find some pathological code that runs much slower on the Athlon than the P4. >Also here is something I found a while back, put it on my page for later >reference. http://speedycpu.dyndns.org/old/p4sucks.html This guy is a moron. He goes on and on about the P4's L1 dcache as if the engineers at Intel all ride the short bus to school and somehow forgot to put some more cache on the chip. Any idiot knows that the P4 has such a small dcache because Intel wanted a cache with a 2 cycle latency instead of the 3 cycle latency of the Athlon and P6. If Intel's measurements and simulations indicated that a 3 cycle cache would be better, don't you think they would have put one in? I mean, it's not like a 3 cycle cache is harder to design than a 2 cycle cache (it's easier) and Intel's done it before, obviously. And if all Intel was after was high clock speeds, putting low latency caches on their chips isn't the way to go about it. If you look at all this guy's points with the mindset of "there must be a reason why they did this" instead of "man are they idiots," it's pretty easy to take apart all of his lame arguments. >>BTW, while I definitely share your enthusiasm for Opteron, I wouldn't get >>people's hopes up with talk of blazing speed. Chess programs run mainly in >>cache, so the on-die memory controller won't help much. Chess programs don't >>require a ton of inter-processor bandwidth, so HT won't help much. Chess >>programs may benefit significantly from x86-64 in the future but high-quality >>x86-64 compilers won't be here for a while. What's left? Some improvements to >>the core, which may or may not be offset by the higher branch mispredict >>penalties, and I doubt they'd make up for the 15+% difference in clock speed >>between the Opteron and the AXP. I expect AMD to ramp up Opteron (and A64) clock >>speeds quickly, so they will be quite good for computer chess, but this week >>won't offer anything mind-bending to computer chess enthusiasts. >> >>-Tom > >Chess engines that use bitboards should get a nice boost. The results I saw from >a Clawhammer running a modified Crafty in linux absolutely annihilated the >AthlonXP MHz for MHz. I'm not talking by 40-50% either.. How does gcc compare to VC or Intel C for Crafty? -Tom
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