Author: Tom Kerrigan
Date: 12:46:11 04/22/03
Go up one level in this thread
On April 22, 2003 at 03:36:33, Anthony Cozzie wrote: >>This guy is a moron. He goes on and on about the P4's L1 dcache as if the >>engineers at Intel all ride the short bus to school and somehow forgot to put >>some more cache on the chip. Any idiot knows that the P4 has such a small dcache >>because Intel wanted a cache with a 2 cycle latency instead of the 3 cycle >>latency of the Athlon and P6. If Intel's measurements and simulations indicated >>that a 3 cycle cache would be better, don't you think they would have put one >>in? I mean, it's not like a 3 cycle cache is harder to design than a 2 cycle >>cache (it's easier) and Intel's done it before, obviously. And if all Intel was >>after was high clock speeds, putting low latency caches on their chips isn't the >>way to go about it. > >While I agree with you (the P4 was designed for multimedia apps and not chess, >and yes, it is good at them) I don't understand this talk about multi-cycle >dcache latencies. I was under the impression that *any* processor that took >more than one cycle to access L1D was horribly slow, and my Athlon MP >optimization guide says that the data cache access is peformed in one pipeline >stage. (P219). > >anthony It probably means that one stage is dedicated to cache access, but that doesn't mean the access only takes one cycle. http://www.xbitlabs.com/articles/cpu/display/athlon64_6.html -Tom
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