Author: Tom Kerrigan
Date: 10:58:50 05/22/03
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On May 21, 2003 at 23:06:05, Eugene Nalimov wrote: >Simplest explanation is that *some* (less critical) resources are split 50-50, >and *some* are not. Somewhere I read (sorry, don't remember where) that P4 has 8 >write buffers. When HT is on, each thread is getting 4 of those, and in rare >cases that can slow thing down even when 2nd thread is absolutely idle. OTOH >L1/L2 cache is shared. > >I assume that Intel split the resources when (1) it simplifies hardware design, >and (2) it would not slow down HT-enabled CPU too much in common cases. > >Thanks, >Eugene Depends on what you mean by critical. Resources like rename registers, instruction window slots, and write combine buffers are split 50-50 when HT is active. These resources seem more critical than anything cache-related to me. Processors can run without cache... When only one thread is run on a HT system, all the resources get merged back to run that one thread, so it's unlikely that a logical processor will be idle and still be decreasing prformance for the other logical processor. It is possible that one thread only uses 1 write combine buffer (out of 6) and the other thread uses 4, but because they only get 3 each, the one that uses 4 is crippled. I believe Intel split the resources to produce a more balanced system. You wouldn't want one logical processor running faster than the other, then you get into asymmetric multiprocessing and OS schedulers would have to be reworked to get good performance. -Tom
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